Time discrete analog to digital conversion of a time dependent analog signal involves sampling of the analog signal by a sample and hold circuit at substantially discrete time points and processing of the sampled analog signals by an analog to digital converter to convert them to digital values.
Such a circuit may be optimized in various ways. High speed conversion may be realized by parallel conversion of samples for different time points. Because the time needed for conversion is longer than the minimal possible time between taking successive samples, this can be done by means of a demultiplexer between the sample and hold circuit and a plurality of analog to digital converters. Offset effects may be eliminated when using differential circuitry, among others by chopping the signal, i.e. conversion when the signal is applied with different polarity. Inter-sample interference may be eliminated by resetting voltages in the circuit between processing signals for different time points.
The application of chopping and demultiplexing to time discrete digital to analog conversion is described in an article by Zwei-Mei Lee et al., titled “A CMOS 15-bit 125-MS/s Time Interleaved ADC With Digital Background Calibration”, published in the IEEE Journal of Solid State circuits, Vol 42, No 10, pages 2149-2160. This article discusses offset calibration of an analog to digital converter (ADC). A differential circuit is used, with a differential amplifier in the sample and hold circuit and ADCs with differential inputs. Switches connect the sample and hold circuit to alternate conversion channels.
A chopper switches the polarity of the connection between the differential amplifier and the differential input of a channel. Each output of the differential amplifier is coupled to each of the differential inputs via first and second switches of the chopper. The first and second switches are alternately made conductive, to reverse the polarity of the coupling from the amplifier to the ADC circuit. Zwei-Mei Lee et al. propose to do this in a pseudo random way during normal operation, to make it possible to determine an offset value from the ADC output, which can be used to correct for the offset. Zwei-Mei Lee et al. combine this with time interleaved conversion by different ADC circuits in parallel, connecting the differential amplifier of the sample and hold circuit alternatively to different ADC conversion pipelines.
In front of the digital output the circuit typically comprises one or more sampling capacitors to retain the analog voltage of the signal. The sample and hold circuit may comprise a differential amplifier to drive inputs of the analog to digital conversion circuits without affecting the sampled voltage on the sampling capacitors. An op amp may be used for example, which is activated in the hold phase of the sample and hold circuit, to copy charge from the sampling capacitors to further sampling capacitors of the conversion circuit.
Amplifier reset is described for example in an article by Wenhua Yang et al., titled “a 3-V 340 mW 14-b 75 Msample/s CMOS ADC With 85-dB SFDR at Nyquist Input”, published in the IEEE Journal of Solid State Circuits, Vol. 36 No 12 pages 1931-1936. Amplifier reset reduces inter sample interference and it improves control of the amplifier's output voltages. Switches connected to the inputs and the outputs of the differential amplifier of the sample and hold circuit are provided, which are made conductive to reset voltages in the circuit. This enables more predictable settling time in the hold phase of operation, and usually faster settling as well, when the voltages start from standard mid values. However, the differential amplifier forms one of the main contributors to power consumption of the circuit, because if has to supply new charging current to its capacitive load at a high rate, for every new sampling time point. The load of the differential amplifier slows down operation.